The present invention relates to a method of manufacturing an electronic device and the electronic device, and more particularly, to a method of manufacturing an electronic device having a structure in which a substrate body and a conductive pattern formed thereon through an insulating layer are connected to each other by using a bump, and the electronic device.
For example, there has variously been provided an electronic apparatus in which an electrode and a conductive pattern are formed on a substrate such as a semiconductor substrate or a glass substrate. As one of types, a semiconductor device referred to as a chip size package has been provided (for example, see Patent Document 1).
The chip size package has a structure in which a rewiring is formed through an insulating layer (a protecting layer) on a surface of a semiconductor chip obtained by dicing a wafer to be a semiconductor substrate on which a device is formed.
In order to manufacture a chip size package disclosed in Patent Document 1, moreover, a plurality of electrodes is first formed on a semiconductor chip region of a semiconductor wafer and a bump is formed on each of the electrodes. The bump is formed through a bonding wire by using a bonding device.
Subsequently, the semiconductor wafer having the bump formed thereon is covered with a resin to be an insulating layer, and furthermore, an upper surface of the bump is exposed from the insulating layer. A conductive pattern (which is also referred to as a rewiring) is formed to be electrically connected to each bump exposed to an upper part of the insulating layer, and furthermore, a solder resist is formed thereon.
Next, a solder ball is formed on the conductive pattern through an opening formed on the solder resist. When the step is ended, a division processing (a dicing processing) is individually carried out over the semiconductor wafer every semiconductor chip region. Consequently, a chip size package is manufactured.
[Patent Document 1]
JP-A-2002-313985
In the chip size package, a periphery of a bonding position of the bump and the conductive pattern is covered with the insulating layer. Moreover, the insulating layer has conventionally had a single layer structure formed by a single material.
For the material of the insulating layer, a high-modulus resin material capable of enhancing an electrical bonding property of the bump and the conductive pattern is generally selected. In the case in which the high-modulus resin material is used for the insulating layer, a reliability of an electrical connection can be enhanced because the bump and the conductive pattern are covered and hardened and are thus protected by a hard resin.
However, the high-modulus resin material generally contracts greatly after heat curing in a formation, causing a problem in that a warpage is generated on a wafer or a chip size package obtained after a division.
On the other hand, as a method of solving the problem of the warpage, it is possible to propose the use of a low-modulus resin as an insulating layer. In general, the low-modulus resin has a smaller contraction after the heat curing than the high-modulus resin material. Therefore, it is possible to suppress the generation of the warpage on the wafer or the chip size package obtained after the division.
When the low-modulus resin is used as the insulating layer, however, a stress is generated between the bump and the conductive pattern. In the worst case, the bump is peeled from the conductive pattern. As a result, there is a problem in that a reliability of an electrical connection is deteriorated greatly.